Carbon nanotube has been demonstrated to have remarkable physical, electrical and thermal properties, and is likely to find numerous applications such as a high-speed and high-density nonvolatile memory. In order to store data, the carbon nanotube is bended to one of two electrodes, which exhibits high voltage or low voltage depending on the bended carbon nanotube.
In FIG. 1A, a prior art of carbon nanotube-based memory circuit including carbon nanotube and sense amplifier is illustrated, as published, U.S. Pat. No. 7,112,493, U.S. Pat. No. 7,115,901 and U.S. Pat. No. 7,113,426. The memory cell 130 is consisted of MOS transfer transistor 132 and carbon nanotube storage element (NT). The transfer gate 132, the drain/source 134 and 135 configure MOS transistor. And storage node (SN), reference node (REF) and release node (RN) configure the storage element. The storage node (SN) is connected to drain/source region 134 of the MOS transistor, carbon nanotube (NT) is connected to reference node (REF), and release node is connected to release line (RL). The word line 131 is connected to the gate 132, and the bit line 136 is connected to the drain/source 135. The bit line 136 is also connected to a sense amplifier 137. The sense amplifier 137 compares the difference of the voltage (or current) between that of bit line 136 and voltage reference (VREF).
The carbon nanotube stores binary states, such as the ON state shown in FIG. 1B and the OFF state shown in FIG. 1C. A small parasitic capacitance exists between SN 151, NT 152 and RN 153. In the ON state as shown in FIG. 1B, NT 152 is flexed and held in close proximity to SN 151 by van der Waals forces, resulting in an ohmic resistance typically in the 1K to 100K ohm range between NT 152 and SN 151. In FIG. 1C, the OFF state has a bended NT 152 on node RN 153, which results in an open circuit, between NT 152 and SN 151. In order to read the stored data “1” (on state), the word line 131 in FIG. 1A is asserted to high level. Thus the bit line 136 is changed by the bended NT 152 as shown in FIG. 1B through MOS access transistor, and then the sense amplifier 137 compares the result with VREF, which is data “1”. In contrast, the bit line 136 is not changed because the storage node SN 151 is isolated from NT 152 when the stored data is “0” (off state), and then the sense amplifier compares the result with VREF, which is data “0”.
Even though the carbon nanotube is ultra fast (100 G˜200 GHz), the access time is mostly determined by the read path through the MOS (Metal Oxide Semiconductor) access transistor and bit line, which path includes contact resistance between carbon nanotube and an electrode. Furthermore, for sensing the bit line voltage without sensing error, the sense amplifier has waiting time until the bit line is changed and reached to enough voltage difference from pre-charged voltage, such as 100 mV˜200 mV. In the large memory array, the charging time (or discharging time) is relatively longer than that of decoding time because the bit line has heavy RC loading with multiple memory cells. Total resistance includes the contact resistance of the bended carbon nanotube, turn-on resistance of MOS access transistor, and resistance of the bit line. Additionally, cell-to-cell and wafer-to-wafer variations affect the sensing time. Hence, the sensing time depends on total resistance and total capacitance of the bit line. And the conventional sense amplifier is relatively big, which reduces cell efficiency.
Moreover, access time is different from location of the selected memory cell in a chip. For example, access time from the sense amp near a data output circuit is faster than that of the sense amp far from the data output circuit, so that it is difficult to latch the sense amp output at high speed, because a latching clock is fixed (not shown). Furthermore, read data line is also heavily loaded for connecting to multiple memory blocks with no buffers, which increases driving current and RC delay time as well.
In this respect, there is still a need for improving the carbon nanotube memory, such that a memory circuit should be re-invented for reading and writing data in the suspended carbon nanotube, which achieves fast access and stable operation. In the present invention, high speed carbon nanotube memory is realized with fast sensing circuit, and a buffered data path is used for writing and reading data. Furthermore, the bit lines are multi-divided to reduce the parasitic capacitance of the bit line. For reading the divided bit line more effectively, multi-stage sense amps are used, such that a small local sense amp is used to insert into the memory array. And a time-domain sensing scheme is introduced, in order to differentiate data “1” and data “0” in a time-domain, and which does not require the conventional sense amp.
The memory cell can be formed on the surface of the wafer. And the steps in the process flow should be compatible within the current CMOS manufacturing environment with additional steps for forming carbon nanotube storage element. Additionally, field-effect aligning process is realized for aligning the carbon nanotubes on exact location of the memory cell, when forming the memory cell. And, the memory cell can be formed from various materials.